JS Engineering, L.L.C.
Integrated Circuit Test Chips for Thermo-Mechanical Evaluation of Electronic Packages
About the firm
JS Engineering, L.L.C. provides integrated circuit test chips designed for the thermo-mechanical evaluation of electronic packages. Based in Auburn, Alabama, the practice specializes in wire bond and flip chip stress test dies that measure complete in-plane and out-of-plane stress states to assess the reliability of semiconductor packaging. It offers calibrated test dies, stress extraction and simulation services, and custom test chip development.
- Team
- Micro
- Firm type
- Materials Testing · Simulation Engineering · Electrical Engineering
Capabilities
Stress Test Chips for Electronic Packages
Service websiteProvides specialized integrated circuit dies designed to evaluate thermo-mechanical stresses within semiconductor packages. These devices assist packaging engineers in measuring both in-plane and out-of-plane stress states to ensure structural integrity and long-term reliability.
- Test Chip Supply
Delivers standard and custom silicon dies in various sizes, ranging from 2.5 mm to 20 mm, to support diverse packaging evaluation needs.
- Test Chip Application
Assists clients with the integration and implementation of sensor dies into packaging workflows for accurate testing.
- Stress Extraction and Simulation
Analyzes raw sensor measurements to extract exact stress state data and run predictive thermo-mechanical simulations.
Calibration Service
Service websiteEstablishes precise sensor coefficients through specialized mechanical testing. This characterization ensures that raw electrical measurements from the stress sensors map accurately to physical stress values.
- Uniaxial Calibration
Applies controlled single-axis mechanical loads to establish sensor sensitivity parameters.
- Hydrostatic Calibration
Subjects sensor dies to uniform fluid pressure to determine hydrostatic stress response coefficients.
- Precision Calibration Fixture Fabrication
Designs and manufactures custom mechanical fixtures required to hold and load dies during calibration procedures.
Custom Test Chip Development
Service websiteEngineers tailored silicon solutions to meet unique packaging dimensions and sensor density requirements. This development covers custom layouts, specialized pad configurations, and targeted sensor placements.
- Wire Bond Stress Test Die
Develops silicon dies configured for wire-bonded packaging, featuring integrated sensor rosettes, diode thermometry, and subsurface full-area heaters.
- Flip Chip Stress Test Die
Engineers perimeter-bumped test dies with precise pitch arrays and high-density sensor rosettes optimized for flip-chip assembly analysis.
Industries
Semiconductors · Electronics · Manufacturing
Projects
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