Custom analog, mixed-signal, and compute-in-memory silicon design
Green Mountain Semiconductor is a specialized semiconductor design services practice delivering custom analog, digital, and mixed-signal silicon solutions. Rooted in memory design and compute-in-memory architectures, it implements complex functionalities and algorithms into proven silicon. The practice supports demanding markets targeting optimized Size, Weight, and Power (SWaP) performance, including aerospace, defense, medical devices, and high-performance computing.
CMMC 2.0 certification
Custom design services spanning analog, digital, and mixed-signal silicon, from transistor-level layout to full ASIC development.
Transistor-level design of critical analog circuits including regulated internal voltages, charge pumps, level shifters, DLLs, PLLs, and A/D and D/A converters.
Integration of analog blocks with digital control logic and high-speed interfaces, utilizing state-of-the-art digital tool flows.
End-to-end ASIC design from initial technology development and prototyping up to test vehicle implementation and yield assessment.
Advanced memory design and emerging non-volatile memory (NVM) development, specializing in ultra-low power in-memory neural networks.
Development of custom compute-in-memory architectures and low-power hardware accelerators for autonomous edge AI inferencing.
Design of standard memory architectures including LPDDR/DDR macro-designs, SRAM macros up to 128MBit, and memory PHY interfaces.
Development and qualification of volatile and non-volatile emerging memories, including STT-MRAM, phase-change memory, and specialty low-temperature DRAM.
Specialized engineering for highly demanding environments requiring optimized size, weight, and power (SWaP) performance.
Radiation-hardened design, ITAR-compliant workflows, and custom memory IP optimized for national security and space applications.
Implementation of 3D-packaging architectures for High Bandwidth Memory (HBM) products and advanced silicon integration.
Development of high-speed interface PHYs based on JEDEC standards, including secondary LPDDR4/4X/5 PHY and SPI/QPI interfaces.
Aerospace · Defense · Medical Devices · Semiconductors · Data Centers
Semiconductors · 2024
Co-developed the NV-1, an ultra-low power ASIC AI processor featuring a non-von-Neumann architecture with parallel combined processor-memory units. This design reduces energy consumption by over 100x and accelerates parallel processing for edge-based untethered devices.
Semiconductors
Developed advanced specialty memory product prototypes, including a 256M LPDDR2-NV and a 32M SPI Flash-replacement chip equipped with integrated error correction code (ECC).